0016 86/02/21 19:30:40 * THE GREAT SCHEMATIC CONTROVERSY               *
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The Cell Library Group has removed the error-prone schematic layer from
the CMOS4 PRIMARY cells because the designer realized that there is no
way to guarantee the schematic layer is 100% correct.  Although this
bold move is facing an extremely strong opposition from almost every
manager in 5K and 5S, the originator was encouraged by Terry Curtis'
"10 Steps to Quality Improvement", one of which is "error-cause removal",
as well as John Roth's policy: "good design is simple design".

The idea is to achieve the ultimate "Idiot-Proof Design System" using
such new-generation CAD tools as FUNDES, TIARA, GALAXY and AUTOLAY along
with CHIPPLOT, and produce chip layout which is correct by construction.
Gone are the days when CALMA and primitive LAYED were the only layout
tools available.  LAYED has evolved over the releases and it can now
read CELLIO table to display cell names, pin locations and pin numbers.
Considering the fact that there is no Design Rule Checker for the
schematic levels, there is no point in checking the chip layout on the
schematic levels if the cell schematic itself contains defects.  Besides,
cooldown has been done only on the composite levels.

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* Our Policy: We will deliver defect-free design *
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